Implementation of Leading Zero Count (LZC) for Arithmetic and Logic Unit (ALU) Operations-Reference-Cited by-同舟云学术

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Implementation of Leading Zero Count (LZC) for Arithmetic and Logic Unit (ALU) Operations

Published:2024-06-21 Issue: Volume:68 Page:1-6
ISSN:
Container-title:2023 4th International Conference on Intelligent Technologies (CONIT)
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Author:

Kumari J. L. V. Ramana¹,Kumar V. Kranthi¹,Abhignya M.¹,Krishna P. Shiva Rama¹

Affiliation:

1. Vignana Jyothi Institute of Engineering and Technology,Department of ECE VNR,Hyderabad,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10625770/10625923/10626583.pdf?arnumber=10626583

Reference14 articles.

1. Performance Analysis of Multicore Processor using FOFO based Approximate Compatible ALU

2. Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs

3. Design and Development of a High-Speed Performance ALU by Using Execution Modes and Multi-Operand Operations;Albishri,2023

4. Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units

5. A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units

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