A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit-Reference-Cited by-同舟云学术

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A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit

Published:2023-10-31 Issue: Volume: Page:
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Container-title:TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON)
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Author:

Ito Shoma¹,Sawada Hisaya¹,Furukawa Hirotaka²,Hokari Naruaki²,Nishiguchi Daishi³,Fukuhara Masaaki¹

Affiliation:

1. Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan

2. School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan

3. Research Institute of Science and Technology, Tokai University,Kumamoto,Japan

Funder

The University of Tokyo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10322307/10322308/10322483.pdf?arnumber=10322483

Reference10 articles.

1. Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

2. Capacitances design method of the main neuron CMOS inverter of a 4-input Variable Logic Circuit with FG calibration;yagi;ICIC Express Letters,2022

3. Analysis by FPD for Neuron CMOS Variable Logic Circuits with FG Calibration;ohtsuka;ICIC Express Lett,2020

4. Study of a Neuron CMOS Variable Logic Circuit with Floating Gate Calibration;ohtsuka;IEEJ,2019

5. Proposal of a Variable Logic Circuit with a Single Output Terminal Using Neuron MOS Transistors;senboku;The IEICE Transactions,2004

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