A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit

Author:

Ito Shoma1,Sawada Hisaya1,Furukawa Hirotaka2,Hokari Naruaki2,Nishiguchi Daishi3,Fukuhara Masaaki1

Affiliation:

1. Graduate School of Information and Telecommunication Engineering, Tokai University,Tokyo,Japan

2. School of Information Telecommunication Engineering, Tokai University,Department of Embedded Technology,Tokyo,Japan

3. Research Institute of Science and Technology, Tokai University,Kumamoto,Japan

Funder

The University of Tokyo

Publisher

IEEE

Reference10 articles.

1. Neuron MOS binary-logic integrated circuits. I. Design fundamentals and soft-hardware-logic circuit implementation

2. Capacitances design method of the main neuron CMOS inverter of a 4-input Variable Logic Circuit with FG calibration;yagi;ICIC Express Letters,2022

3. Analysis by FPD for Neuron CMOS Variable Logic Circuits with FG Calibration;ohtsuka;ICIC Express Lett,2020

4. Study of a Neuron CMOS Variable Logic Circuit with Floating Gate Calibration;ohtsuka;IEEJ,2019

5. Proposal of a Variable Logic Circuit with a Single Output Terminal Using Neuron MOS Transistors;senboku;The IEICE Transactions,2004

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