Author:
Sklyarov Valery,Skliarova Iouliia,Silva Joao,Sudnitson Alexander
Cited by
9 articles.
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1. A Programmable 5G DU-RU SmartNIC based on MPSoC FPGA;2024 IEEE 25th International Conference on High Performance Switching and Routing (HPSR);2024-07-22
2. Accelerating CPU to Memory Access in SoC Architecture Design;SoutheastCon 2024;2024-03-15
3. Investigation of Communication Overhead of SoC Lookaside Accelerators;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
4. Characterization of a Coherent Hardware Accelerator Framework for SoCs;Lecture Notes in Computer Science;2023
5. Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device;2019 29th International Conference on Field Programmable Logic and Applications (FPL);2019-09