1. Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Small Logic-based Multipliers with Incomplete Sub-Multipliers for FPGAs;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
3. Multiplier Architecture with a Carry-Based Partial Product Encoding;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
4. Efficient Soft Core Multiplier for Post Quantum Digital Signatures;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
5. Efficient implementation of signed multipliers on FPGAs;Computers and Electrical Engineering;2024-05