Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine-Reference-Cited by-同舟云学术

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine

Published:2024-07 Issue:7 Volume:59 Page:2055-2069
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Prasad Arpan Suravi¹^ORCID,Scherer Moritz¹^ORCID,Conti Francesco²^ORCID,Rossi Davide²^ORCID,Di Mauro Alfio¹^ORCID,Eggimann Manuel¹^ORCID,Gómez Jorge Tomás³^ORCID,Li Ziyun³^ORCID,Sarwar Syed Shakib³^ORCID,Wang Zhao³,De Salvo Barbara³^ORCID,Benini Luca¹^ORCID

Affiliation:

1. Integrated Systems Laboratory, ETH Zürich, Zürich, Switzerland

2. Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy

3. Meta Reality Labs, Burlingame, CA, USA

Funder

Meta Reality Labs

Chips Joint Undertaking project TRISTAN

Chips Joint Undertaking project ISOLDE

Spoke 1 on Future HPC of the Italian Research Center on High-Performance Computing, Big Data and Quantum Computing (ICSC) funded by MUR Mission 4—Next Generation EU

Convolve project evaluated by the EU Horizon Europe

Swiss State Secretariat for Education Research and Innovation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/4/10575937/10538116.pdf?arnumber=10538116

Reference35 articles.

1. Creating the future: Augmented reality, the next human–machine interface;Abrash

2. MEgATrack

3. Real-time gaze tracking with event-driven eye segmentation;Feng

4. 9.6 A 1/2.3 inch 12.3 Mpixel with on-chip 4.97 TOPS/W CNN processor back-illuminated stacked CMOS image sensor;Eki

5. Marsellus: A heterogeneous RISC-V AI-IoT end-node SoC with 2–8 b DNN acceleration and 30%-boost adaptive body biasing;Conti;IEEE J. Solid-State Circuits,2023