A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping-Reference-Cited by-同舟云学术

A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping

Published:2022-07 Issue:7 Volume:57 Page:2078-2089
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Li Hanyue¹^ORCID,Shen Yuting¹^ORCID,Xin Haoming¹^ORCID,Cantatore Eugenio¹^ORCID,Harpe Pieter¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

Funder

Dutch Research Council

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9809766/09766432.pdf?arnumber=9766432

Reference30 articles.

1. A 250kHz-BW 93dB-SNDR 4\textrmth-order noise-shaping SAR using capacitor stacking and dynamic buffering;liu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

2. A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

3. Thermal Noise in Track-and-Hold Circuits: Analysis and Simulation Techniques

4. A Discrete-Time Audio $\Delta\Sigma$ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques

5. An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

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