A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
Author:
Affiliation:
1. ICTEAM Institute, Université catholique de Louvain (UCLouvain), Louvain-la-Neuve, Belgium
Funder
Fonds de la Recherche Scientifique (FRS-FNRS) of Belgium
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10192489/10040689.pdf?arnumber=10040689
Reference28 articles.
1. An MOS transistor model for analog circuit design
2. A 0.9-nA Temperature-Independent 565-ppm/°C Self-Biased Current Reference in 22-nm FDSOI
3. Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs
4. Systematic Design of Analog CMOS Circuits
5. A CMOS 0.85-V 15.8-nW Current and Voltage Reference without Resistors
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1. A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/$^\circ$C CMOS-Only Current Reference in 0.11-$\mu$m Bulk and 22-nm FD-SOI;IEEE Journal of Solid-State Circuits;2024
2. A nA-Range Area-Efficient Sub-100-ppm/$^\circ$C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI;IEEE Journal of Solid-State Circuits;2024
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