A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference-Reference-Cited by-同舟云学术

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

Published:2023-07 Issue:7 Volume:58 Page:2109-2124
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Sehgal Rishabh¹^ORCID,Thareja Tanmay¹^ORCID,Xie Shanshan¹^ORCID,Ni Can¹,Kulkarni Jaydeep P.¹^ORCID

Affiliation:

1. Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10164681/10032490.pdf?arnumber=10032490

Reference44 articles.

1. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications

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3. Designing Hardware for Machine Learning: The Important Role Played by Circuit Designers

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5. A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training

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