A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM-Reference-Cited by-同舟云学术

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A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM

Published:2024 Issue: Volume: Page:1-10
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Tan Fei¹^ORCID,Yu Wei-Han¹^ORCID,Lin Jinhai¹^ORCID,Un Ka-Fai¹^ORCID,Martins Rui P.²^ORCID,Mak Pui-In¹^ORCID

Affiliation:

1. Institute of Microelectronics, Faculty of Science and Technology-ECE, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

2. Institute of Microelectronics, Faculty of Science and Technology, ECE, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

Funder

Macau Science and Technology Development Fund (FDCT), Macau Special Administrative Region

New Cornerstone Science Foundation through XPLORER PRIZE

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/4/4359912/10638323.pdf?arnumber=10638323

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Review of Sub- μ W CMOS Analog Computing Circuits for Instant 1-Dimensional Audio Signal Processing in Always-On Edge Devices;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

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