RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator

Author:

Li ZiyunORCID,Wang ZhehongORCID,Xu LiORCID,Dong QingORCID,Liu Bowen,Su Chin-I,Chu Wen-Ting,Tsou George,Chih Yu-Der,Chang Tsung-Yung Jonathan,Sylvester DennisORCID,Kim Hun-SeokORCID,Blaauw DavidORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02

2. Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks;IEEE Transactions on Computers;2024-01

3. Intrusion Detection System with H2O Deep Learning Approach;2023 17th International Conference on Telecommunication Systems, Services, and Applications (TSSA);2023-10-12

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5. Design memristor-based computing-in-memory for AI accelerators considering the interplay between devices, circuits, and system;Science China Information Sciences;2023-07-04

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