A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS-Reference-Cited by-同舟云学术

A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS

Published:2023-05 Issue:5 Volume:58 Page:1386-1399
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Megahed Mohamed¹^ORCID,Anand Tejasvi¹^ORCID

Affiliation:

1. Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA

Funder

Center for Design of Analog-Digital Integrated Circuits

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/10042409.pdf?arnumber=10042409

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5. A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor

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