A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada
Funder
Natural Sciences and Engineering Research Council of Canada
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/10262388/10136699.pdf?arnumber=10136699
Reference16 articles.
1. Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS
2. A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of −246dB for IoT applications in 65nm CMOS
3. High-speed CMOS circuit technique
4. A 24-GHz Receiver Frontend With an LO Signal Generator in 0.18-$\mu$m CMOS
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