A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator

Author:

Shen Hsueh-Yen1,Lee Yu-Chi1ORCID,Tong Tzu-Wei1,Yang Chia-Hsiang2ORCID

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

2. Department of Electrical Engineering and the Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

Funder

Ministry of Science and Technology, Taiwan

Intelligent and Sustainable Medical Electronics Research Fund in National Taiwan University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference23 articles.

1. A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices

2. UNPU: An energy-efficient deep neural network accelerator with fully variable weight bit precision;lee;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018

3. A 91 mW 90 fps super-resolution processor for full HD images;shen;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

4. Training-based super-resolution algorithm using K-means clustering and detail enhancement;jeong;Proc Eur Signal Process Conf,2010

5. Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods

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1. Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies;ACM Transactions on Architecture and Code Optimization;2024-07-12

2. USR-LUT: A High-Efficient Universal Super Resolution Accelerator with Lookup Table;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

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