A Low-Power, Compact, 0.1–5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR
Author:
Affiliation:
1. State Key Laboratory of ASIC and System, Fudan University, Shanghai, China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/4/10648889/10491139.pdf?arnumber=10491139
Reference40 articles.
1. Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference
2. A 3–6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P1dB and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications
3. Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications
4. Effect of Out-of-Band Blockers on the Required Linearity, Phase Noise, and Harmonic Rejection of SDR Receivers Without Input SAW Filter
5. A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
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