An Efficient Hardware Architecture for Activation Function in Deep Learning Processor-Reference-Cited by-同舟云学术

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An Efficient Hardware Architecture for Activation Function in Deep Learning Processor

Published:2018-06 Issue: Volume: Page:
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Container-title:2018 IEEE 3rd International Conference on Image, Vision and Computing (ICIVC)
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Author:

Li Lin,Zhang Shengbing,Wu Juan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8476690/8492718/08492754.pdf?arnumber=8492754

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs;Microelectronics Journal;2024-09

2. A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. VLUT: Design and Evaluation of Variable band LUT to realize Activation Functions;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

4. Flex-SFU: Accelerating DNN Activation Functions by Non-Uniform Piecewise Approximation;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

5. ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-07

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