FPGA Implementation of MAC Unit for Artificial Neural Network Accelerators
Author:
Affiliation:
1. University of Kufa,Dep. Electronic and Communication Engineering,Najaf,Iraq
2. University of Kufa,IT Research and Development Center,Dep. Electronic and Communication Engineering,Najaf,Iraq
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10412853/10412862/10413151.pdf?arnumber=10413151
Reference18 articles.
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5. Design of Floating-Point MAC Unit for Computing DNN Applications in PIM
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Implementation of a Parameterized Elastic Deep Neural Network Accelerator with a 32-Bit Floating-Point Number Using FPGA;2023 International Conference on Modeling & E-Information Research, Artificial Learning and Digital Applications (ICMERALDA);2023-11-24
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