1. Design of vedic multiplier using area efficient carry select adder (IEEE) in the year 2015;gokhale,0
2. VLSI implementation of multiplier design using reversible logic gate
3. Implementation of high-speed hybrid Carry Select Adder using Binary to Excess-1 Converter;srinithraavi,2022
4. Vedic Mathematics;bharati krsna tirthaji,0
5. Vedic Mathematics Made Easy;bathia,0