Optimization of Photodiode Design Through Analysis of Full-Well Capacity and Image Lag in 0.5 <i>μ</i>m CMOS Image Sensors With Vertical Transfer Gates-Reference-Cited by-同舟云学术

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Optimization of Photodiode Design Through Analysis of Full-Well Capacity and Image Lag in 0.5 μm CMOS Image Sensors With Vertical Transfer Gates

Published:2022-10 Issue:10 Volume:43 Page:1697-1700
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Park Jae Hyeon¹,Suk Chan Hee¹,Kim Sungchul²,Kim Jae Ho²,Kwon Uihui²,Kim Dae Sin²,Yoo Keon-Ho³^ORCID,Kim Tae Whan¹^ORCID

Affiliation:

1. Department of Electronics Engineering, Hanyang University, Seoul, South Korea

2. Innovation Center, Device Solution Business, Computational Science and Engineering Team, Samsung Electronics Company Ltd., Hwasung-si, Republic of Korea

3. Department of Physics, Research Institute for Basic Sciences, Kyung Hee University, Seoul, South Korea

Funder

Samsung Electronics Company Ltd

National Research Foundation of Korea (NRF) Grants through the Korea Government Ministry of Science and ICT

NRF

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/9903996/09864613.pdf?arnumber=9864613

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