Low Temperature Cu-Cu Bonding Using an Intermediate Sacrificial Sn Layer
Author:
Affiliation:
1. School of Integrated Circuits, Tsinghua University, Beijing, China
2. School of Integrated Circuits and the Beijing Innovation Center for Future Chips, Tsinghua University, Beijing, China
Funder
Natural Science Foundation of China
Beijing Natural Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/55/10001839/09945943.pdf?arnumber=9945943
Reference21 articles.
1. Novel Cu-to-Cu Bonding With Ti Passivation at 180$^{\circ}{\rm C}$ in 3-D Integration
2. Improvement of Wafer-Level Cu-to-Cu Bonding Quality Using Wet Chemical Pretreatment
3. Low-Temperature (70°C) Cu-to-Cu Direct Bonding by Capping Metal Layers
4. Demonstration and Electrical Performance of Cu–Cu Bonding at 150 °C With Pd Passivation
5. Room temperature metal direct bonding
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1. Simultaneously performing interlayer copper interconnecting and TSV filling in stacked chips at room temperature based on copper electroplating;AIP Advances;2024-07-01
2. Fine Pitch Wafer-to-Wafer Hybrid Bonding for Three-Dimensional Integration;2023 24th International Conference on Electronic Packaging Technology (ICEPT);2023-08-08
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