Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications-Reference-Cited by-同舟云学术

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

Published:2022-05 Issue:5 Volume:43 Page:674-677
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Kao K.-H.¹^ORCID,Godfrin C.²,Elsayed A.²,Li R.²^ORCID,Simoen E.²^ORCID,Grill A.²^ORCID,Kubicek S.²,Radu I. P.²^ORCID,Govoreanu B.²

Affiliation:

1. Department of Electrical Engineering and the Center for Quantum-Frontiers of Research and Technology, National Cheng Kung University, Tainan, Taiwan

2. imec, Leuven, Belgium

Funder

imec through the Quantum Computing imec Industrial Affiliation Program

European Union’s Horizon 2020 Research and Innovation Program

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/9762988/09743910.pdf?arnumber=9743910

Reference36 articles.

1. Sidewall damage in plasma etching of Si/SiGe heterostructures

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3. Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

4. Impact of thermal budget on the low-frequency noise of DRAM peripheral nMOSFETs

5. Observation of percolation-induced two-dimensional metal-insulator transition in a Si MOSFET

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