An Efficient Application Specific Instruction Set Processor for Multi-tone Digital Halftoning-Reference-Cited by-同舟云学术

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An Efficient Application Specific Instruction Set Processor for Multi-tone Digital Halftoning

Published:2022-01-14 Issue: Volume: Page:
ISSN:
Container-title:2022 2nd International Conference on Consumer Electronics and Computer Engineering (ICCECE)
language:
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Author:

Liu Zhili¹,Jiang Hao²,Zheng Dandan¹,Huang Kai³,Xiong Dongliang⁴,Jiang Xiaowen²

Affiliation:

1. Hangzhou Sec-Chip Technology Co, Ltd,Hangzhou,China

2. College of Information Science & Electronic Engineering, Zhejiang University,Hangzhou,China

3. School of Micro-Nano Electronics, Zhejiang University,Hangzhou,China

4. College of Electrical Engineering, Zhejiang University,Hangzhou,China

Funder

National Key R&D Program of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9712655/9712656/09712838.pdf?arnumber=9712838

Reference11 articles.

1. Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2. An FPGA implementation of chaotic and edge enhanced error diffusion

3. An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation

4. Adaptive Optimization Design of Vector Error Diffusion Algorithm and IP Core for FPGA

5. An Application Specific Vector Processor for CNN-Based Massive MIMO Positioning

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