Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Computer Science,Control and Systems Engineering
Link
http://xplorestaging.ieee.org/ielx7/4563995/7112557/07072514.pdf?arnumber=7072514
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05
2. Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs;ACM Transactions on Design Automation of Electronic Systems;2022-02-12
3. A Review of Spatial Exploration of FPGA Design;Computer Science and Application;2022
4. Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support;2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2021-07
5. SSSL: Secure Search Space Locking of Behavioral IPs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
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