Power and Area-Efficient XNOR-AND Hybrid Binary Neural Networks Using TFT-Type Synaptic Device-Reference-Cited by-同舟云学术

Power and Area-Efficient XNOR-AND Hybrid Binary Neural Networks Using TFT-Type Synaptic Device

Published:2023-02 Issue:2 Volume:44 Page:325-328
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Lee In-Seok¹^ORCID,Kim Hyeongsu¹^ORCID,Park Min-Kyu¹^ORCID,Hwang Joon¹^ORCID,Koo Ryun-Han¹,Kim Jae-Joon¹^ORCID,Lee Jong-Ho¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Funder

Technology Innovation Program funded by the Ministry of Trade, Industry & Energy

BK21 FOUR program of the Education and Research Program for Future ICT Pioneers

by Institute of Information & communications Technology Planning & Evaluation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10027614/09987486.pdf?arnumber=9987486

Reference17 articles.

1. XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

2. Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or ?1;courbariaux;arXiv 1602 02830 [cs],2016

3. Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks

4. Binary convolutional neural network on RRAM

5. Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

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