Suppression on Crosstalk Voltages of Paralleled SiC MOSFETs with Optimized Gate Configurations and Additional SiC SBDs
Author:
Affiliation:
1. Xi'an Jiaotong University,School of Electrical Engineering,Xi’an,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10215093/10215083/10215177.pdf?arnumber=10215177
Reference6 articles.
1. Comparative Investigation on Paralleling Suitability for SiC MOSFETs and SiC/Si Cascode Devices
2. A Low-Cost Novel Structure for Paralleled SiC JFET/Si MOSFET Cascodes to Balance Turn-on Current and Junction Temperature
3. Simulation and Characterization of Cross-Turn-On Inside a Power Module of Paralleled SiC MOSFETs
4. A Method to Balance Dynamic Current of Paralleled SiC MOSFETs With Kelvin Connection Based on Response Surface Model and Nonlinear Optimization
5. Effect of Asymmetric Layout and Unequal Junction Temperature on Current Sharing of Paralleled SiC MOSFETs with Kevin-Source Connection;zhao;IEEE Transactions on Power Electronics,2019
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