Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor-Reference-Cited by-同舟云学术

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Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor

Published:2022-06-27 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
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Author:

Leplus Gaetan¹,Savry Olivier¹,Bossuet Lilian²

Affiliation:

1. LETI, CEA,Grenoble,France

2. Jean Monnet University,Laboratoire Hubert Curien,Saint-Etienne,France

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9839666/9839669/09840060.pdf?arnumber=9840060

Reference11 articles.

1. Differential Power Analysis in the Presence of Hardware Countermeasures

2. Differential Fault Intensity Analysis

3. Non-deterministic Processors

4. Hardware Countermeasures against DPA – A Statistical Analysis of Their Effectiveness

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