A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $\mu$m CMOS Technology
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics
Link
http://xplorestaging.ieee.org/ielx5/7260/5196837/05175439.pdf?arnumber=5175439
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 24-to-30 GHz Ultra-High-Linearity Down-Conversion Mixer for 5G Applications Using a New Linearization Method;Sensors;2022-05-17
2. RF CMOS Double Balanced Gilbert Cell Mixer for 5G Application;2021 3rd International Conference on Signal Processing and Communication (ICPSC);2021-05-13
3. Achieving high linearity and conversion gain in double balanced mixer with cascoded RF and LO stage;Analog Integrated Circuits and Signal Processing;2021-01-02
4. Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits;IEICE Electronics Express;2020
5. A 45- to 64-GHz ultra-low-power and low-LO-power sub-harmonic down-conversion mixer with merged self-biased trans-impedance amplifier in 90-nm CMOS;Microwave and Optical Technology Letters;2017-06-27
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