Beating in-order stalls with "flea-flicker" two-pass pipelining-Reference-Cited by-同舟云学术

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Beating in-order stalls with "flea-flicker" two-pass pipelining

Published:2006-01 Issue:1 Volume:55 Page:18-33
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Barnes R.D.,Sias J.W.,Nystrom E.M.,Patel S.J.,Navarro J.,Hwu W.W.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/32984/01545748.pdf?arnumber=1545748

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Survey on the Proposed Architectures for Efficient Execution of Irregular Applications Using Pipeline Parallelism;2023 Congress in Computer Science, Computer Engineering, & Applied Computing (CSCE);2023-07-24

2. Specially-Designed Out-of-Order Processor Architecture for Microcontrollers;Electronics;2022-09-21

3. Revisiting Using the Results of Pre-Executed Instructions in Runahead Processors;IEEE Computer Architecture Letters;2014-07-16

4. Discerning the dominant out-of-order performance advantage;ACM SIGPLAN Notices;2013-04-23

5. Discerning the dominant out-of-order performance advantage;ACM SIGARCH Computer Architecture News;2013-03-29

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