A 14-transistor CMOS full adder with full voltage-swing nodes

Author:

Vesterbacka M.

Publisher

IEEE

Cited by 45 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Low Power and High Speed 1-bit Full Adder for DSP Applications;2024 International Conference on Advancements in Power, Communication and Intelligent Systems (APCI);2024-06-21

2. A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

3. Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

4. A Novel 1-bit Fast and Low Power 19-T Full Adder Circuit at 45 nm Technology Node;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24

5. Performance Efficient and Fault Tolerant Approximate Adder;Journal of Electronic Testing;2023-12

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