Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test-Reference-Cited by-同舟云学术

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Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test

Published:2023-02 Issue:1 Volume:40 Page:96-104
ISSN:2168-2356
Container-title:IEEE Design & Test
language:
Short-container-title:IEEE Des. Test

Author:

Ravelo Blaise¹^ORCID,Douyere Alexandre²^ORCID,Liu Yang³,Rahajandraibe Wenceslas⁴^ORCID,Wan Fayu¹^ORCID,Chan George⁵^ORCID,Guerin Mathieu⁴

Affiliation:

1. Nanjing University of Information Science and Technology (NUIST), Nanjing, China

2. Energy Laboratory, Network and Telecom Team University of la Reunion, La Reunion Island, France

3. Altran, Vélizy-Villacoublay, France

4. Aix Marseille University, Université de Toulon CNRS, IM2NP, Marseille, France

5. ASM Pacific Technology Ltd, Tsing Yi, Hong Kong

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/6221038/10024350/09745935.pdf?arnumber=9745935

Reference28 articles.

1. Generic linear RC delay modeling for digital CMOS circuits

2. The Elmore delay as a bound for RC trees with generalized input signals

3. Closed-Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs for RC Trees

4. A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect

5. Equivalent Elmore delay for RLC trees

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