SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs
Author:
Affiliation:
1. Columbia University, New York, NY, USA
2. Harvard University, Cambridge, MA, USA
Funder
Defense Advanced Research Projects Agency
Army Research Office
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/6221038/10288420/10234535.pdf?arnumber=10234535
Reference20 articles.
1. A 12 nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800 MHz multi-plane NoC;jia;Proc IEEE Eur Solid-State Circuits Conf,2022
2. IEEE Standard Test Access Port and Boundary Scan Architecture
3. Agile SoC development with open ESP
4. INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design
5. Virtual channels vs. multiple physical networks
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