Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications

Author:

Eyerman Stijn,Du Bois Kristof,Eeckhout Lieven

Publisher

IEEE

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Novel AI Based Approach for Performance validation;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

2. Splash-4: A Modern Benchmark Suite with Lock-Free Constructs;2022 IEEE International Symposium on Workload Characterization (IISWC);2022-11

3. DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks;2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2022-05

4. Scale-Model Architectural Simulation;2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2022-05

5. Automatic Identification and Precise Attribution of DRAM Bandwidth Contention;49th International Conference on Parallel Processing - ICPP;2020-08-17

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