An Improved Delay Cell with Low Power Consumption and Strong Driving Capability-Reference-Cited by-同舟云学术

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An Improved Delay Cell with Low Power Consumption and Strong Driving Capability

Published:2023-10-24 Issue: Volume: Page:1-4
ISSN:
Container-title:2023 IEEE 15th International Conference on ASIC (ASICON)
language:
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Author:

Tian Cai¹,Wu Tianxiang¹,Ma Shunli¹,Bao Wenzhong¹

Affiliation:

1. Fudan University,State Key Laboratory of Integrated Chips and Systems,Shanghai,China

Funder

National Natural Science Foundation of China

Natural Science Foundation of Shanghai

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10395907/10395930/10396562.pdf?arnumber=10396562

Reference6 articles.

1. CMOS VLSI Design: A Circuits and Systems Perspective;Weste;Pearson,2010

2. A Comparison of Broadband and Tunable Delay-Line Structures in 45-nm CMOS

3. A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS

4. An active analog delay and the delay reference loop

5. 0.18-/spl mu/m CMOS equalization techniques for 10-Gb/s fiber optical communication links

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