Author:
Seo Young-Suk,Lee Jang-Woo,Kim Hong-Jung,Yoo Changsik,Lee Jae-Jin,Jeong Chun-Seok
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
12 articles.
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1. A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-08
2. A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE;2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID);2016-01
3. A novel approach to analysis and design of bang-bang CDR circuits;COMPEL - The international journal for computation and mathematics in electrical and electronic engineering;2013-11-11
4. Modeling of jitter in bang‐bang clock and data recovery circuits;COMPEL - The international journal for computation and mathematics in electrical and electronic engineering;2013-05-03
5. Modeling of Jitter in Bang-Bang CDR With Fourier Series Analysis;IEEE Transactions on Circuits and Systems I: Regular Papers;2013-01