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A 0.67- $\mu\text{W}$ 177-ppm/°C All-MOS Current Reference Circuit in a 0.18- $\mu\text{m}$ CMOS Technology

  • Published:2016-08 Issue:8 Volume:63 Page:723-727
  • ISSN:1549-7747
  • Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chouhan Shailesh Singh,Halonen Kari

Funder

Project AUTOVOLT of the Academy of Finland

Project EFFINANO of the Aalto University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 36 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A PVT-Robust Beta-Multiplier Current Reference with Body-Effect-Based Temperature Dependency Modulation;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

2. A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

3. A nA-Range Area-Efficient Sub-100-ppm/$^\circ$C Peaking Current Reference Using Forward Body Biasing in 0.11-$\mu$m Bulk and 22-nm FD-SOI;IEEE Journal of Solid-State Circuits;2024

4. Ultra-Low-Power Sub-1 V 29 ppm/°C Voltage Reference and Shared-Resistive Current Reference;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03

5. A 79 pW, 106 ppm/°C NMOS-only current reference with leakage current isolation based on body bias technique;AEU - International Journal of Electronics and Communications;2023-03
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