A low-power inverted ladder D/a converter
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/8920/34441/01643469.pdf?arnumber=1643469
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 0.002‐mm 2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC);IET Circuits, Devices & Systems;2021-04-08
2. Nonlinearity analysis of folded Multi-LSB decided resistor string digital to analog converter;Analog Integrated Circuits and Signal Processing;2011-07-21
3. A 0.13-$\mu{\hbox {m}}$ 1-GS/s CMOS Discrete-Time FFT Processor for Ultra-Wideband OFDM Wireless Receivers;IEEE Transactions on Microwave Theory and Techniques;2011-06
4. A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-11
5. A 10-bit Low-Power Small-Area High-Swing CMOS DAC;IEEE Transactions on Nuclear Science;2010-02
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