A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero

Author:

Tseng Wei-Hsin,Wu Jieh-Tsorng,Chu Yung-Cheng

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Dynamic Switching Compensation Technique Mitigating Code-Dependent Switching Distortion in CS-DACs;2022 IEEE 19th India Council International Conference (INDICON);2022-11-24

3. A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications;2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2021-07

4. Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021-02

5. A 14 bit 3GS/s DAC Achieving SFDR >63dB up to 1.4GHz with Random Differential-Quad Switching technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2021

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