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A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance

  • Published:2021-01 Issue:1 Volume:68 Page:161-165
  • ISSN:1549-7747
  • Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
  • language:
  • Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Chang Shun-ChiORCID,Liu Shen-IuanORCID

Funder

TSMC University- Shuttle Program

Genesys Logic Inc

Intelligent and Sustainable Medical Electronics Research Fund in National Taiwan University

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector;2023 20th International SoC Design Conference (ISOCC);2023-10-25

2. Design of Digital Phase Interpolator for 6.25Gbps CDR Circuit;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20

3. A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit;Journal of Circuits, Systems and Computers;2022-04-04

4. A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface;IEEE Solid-State Circuits Letters;2022

5. A 2.7-Gb/s Multiplexed-DLL-Based CDR Circuit for ±10% Clock-Embedded Spread-Spectrum Modulation Depth;2021 IEEE Asian Solid-State Circuits Conference (A-SSCC);2021-11-07
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