0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array-Reference-Cited by-同舟云学术

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0.3 pJ/Bit Machine Learning Resistant Strong PUF Using Subthreshold Voltage Divider Array

Published:2020-08 Issue:8 Volume:67 Page:1394-1398
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Venkatesh Abilash^ORCID,Venkatasubramaniyan Aishwarya Bahudhanam,Xi Xiaodan^ORCID,Sanyal Arindam^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9152175/08846235.pdf?arnumber=8846235

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Modeling Attack Tests and Security Enhancement of the Sub-Threshold Voltage Divider Array PUF;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

2. PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling;IEICE Electronics Express;2024-01-25

3. A Reconfigurable SRAM CRP PUF with High Reliability and Randomness;Electronics;2024-01-10

4. A Lightweight Authentication Protocol Against Modeling Attacks Based on a Novel LFSR-APUF;IEEE Internet of Things Journal;2024-01-01

5. Dynamic self-test scheme and authentication protocol for improving robustness of strong PUF;Microelectronics Journal;2023-09

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