Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC-Reference-Cited by-同舟云学术

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Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

Published:2010-08 Issue:8 Volume:57 Page:607-611
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

U-Fat Chio ,He-Gong Wei ,Yan Zhu ,Sai-Weng Sin ,Seng-Pan U ,Martins R P,Maloberti Franco

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/8920/5550279/05497109.pdf?arnumber=5497109

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Successive-approximation-register ADC Implementation in 180 nm CMOS Technology for Bio-medical Applications;2023 IEEE Symposium on Computers & Informatics (ISCI);2023-10-14

2. A 1.67 pJ/Conversion-step 8-bit SAR-Flash ADC Architecture in 90-nm CMOS Technology;International Journal of Electronics and Telecommunications;2023-07-26

3. NTC thermistor nonlinearity compensation using wheatstone bridge and novel dual-stage single-flash piecewise-linear ADC;Metrology and Measurement Systems;2023-07-26

4. A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC;IEEE Transactions on Biomedical Circuits and Systems;2023-02

5. A 10-bit 30MS/s Subranging SAR ADC with a Triple Reference Voltage Technique;2020 International Symposium on Computer, Consumer and Control (IS3C);2020-11

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