Optimizing Off-Chip Memory Access for Deep Neural Network Accelerator
Author:
Affiliation:
1. Aerospace Information Research Institute (formerly Institute of Electronics), Chinese Academy of Sciences, Beijing, China
2. Technology R&D Centre, Shandong Industrial Institute of Integrated Circuits Technology Ltd., Jinan, China
Funder
National Natural Science Foundation of China
Major Program of Beijing Science and Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9741739/09708433.pdf?arnumber=9708433
Reference16 articles.
1. SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators
2. ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
3. Ramulator: A Fast and Extensible DRAM Simulator
4. What Your DRAM Power Models Are Not Telling You
5. Very deep convolutional networks for large-scale image recognition;simonyan;arXiv 1409 1556,2014
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