A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method-Reference-Cited by-同舟云学术

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A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

Published:2015-05 Issue:5 Volume:62 Page:451-455
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kim Jong-Boo,Hong Seong-Kwan,Kwon Oh-Kyong

Funder

Image Frontier Center (IFC) and Samsung Electronics Co. Ltd.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/7094329/07001248.pdf?arnumber=7001248

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1. A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit;Sensors;2024-06-05

2. Digital Background Calibration Assisted with Noise-Shaping for a 10-b Bridged SAR ADC;Journal of Circuits, Systems and Computers;2024-03-05

3. A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors;Integration;2023-07

4. A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-05

5. A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure;IEEE Journal of the Electron Devices Society;2022

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