High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx5/8920/35981/01705065.pdf?arnumber=1705065
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1. Design Techniques for optimizing an Adaptive Decision Feedback Equalizer for 5G Communication;2024 International Conference on Knowledge Engineering and Communication Systems (ICKECS);2024-04-18
2. A Distributed Arithmetic based realization of the Least Mean Square Adaptive Decision Feedback Equalizer with Offset Binary Coding scheme;Signal Processing;2021-08
3. High-Throughput and Improved-Convergent Design of Pipelined Adaptive DFE for 5G Communication;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-02
4. High performance area efficient DA based FIR filter for concurrent decision feedback equalizer;International Journal of Speech Technology;2020-03-03
5. Adopting a low hardware redesigned architectural design for educational environment by using DFE-based 5G communication;International Journal of Electrical Engineering & Education;2019-03-21
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