Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications
Author:
Affiliation:
1. Department of Engineering and Architecture, University of Parma, Parma, Italy
2. Compute System Architecture (CSA), imec, Leuven, Belgium
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9809796/09773348.pdf?arnumber=9773348
Reference36 articles.
1. XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
2. Deep Learning with Low Precision by Half-Wave Gaussian Quantization
3. Time-Multiplexed Flash ADC for Deep Neural Network Analog in-Memory Computing
4. A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations
5. Improving Accuracy of Binary Neural Networks using Unbalanced Activation Distribution
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2. Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications;IEEE Journal on Exploratory Solid-State Computational Devices and Circuits;2023-12
3. Modelling and Optimization of a Mixed-Signal Accelerator for Deep Neural Networks;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03
4. A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18
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