Hardware Implementation of Low Complexity High-speed Perceptron Block
Author:
Affiliation:
1. IIT Guwahati,Dept. of EEE,Assam,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937758.pdf?arnumber=9937758
Reference11 articles.
1. The hardware structure design of perceptron with FPGA implementation
2. Performance Comparison of Multi-layer Perceptron (Back Propagation, Delta Rule and Perceptron) algorithms in Neural Networks
3. Hardware Implementation of Sigmoid Activation Functions using FPGA
4. An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System
5. Multi-layer perceptron (MLP) neural network technique for offline handwritten Gurmukhi character recognition
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