A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration-Reference-Cited by-同舟云学术

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A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration

Published:2022-05-28 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Lan Jingchao¹,Zhai Danfeng¹,Chen Yongzhen²,Ni Zhekan³,Shen Xingchen¹,Ye Fan¹,Ren Junyan¹

Affiliation:

1. Fudan University,State Key Laboratory of ASIC & System,dept. Microelectronics,Shanghai,China

2. Tongji University,College of electronic and information engineering,Shanghai,China

3. Hangzhou Dianzi University,The electronics and information college,Hangzhou,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937296.pdf?arnumber=9937296

Reference14 articles.

1. A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

2. Ring Amplifiers for Switched Capacitor Circuits

3. A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers

4. A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier

5. Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-06-12

2. A 12-bit 2.32GS/s pipelined/SAR hybrid ADC with a high-linearity input buffer;IEICE Electronics Express;2023-12-10

3. A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

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