An Overshoot Voltage Reduction Technique with Improved Speed for Zero-Crossing Detector in Pipeline ADCs
Author:
Affiliation:
1. Sabanci University,Faculty of Engineering and Natural Sciences,Istanbul,Turkey
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937960.pdf?arnumber=9937960
Reference10 articles.
1. A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration
2. A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC
3. Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp
4. A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
5. A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level Shifting
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