A 19-bit Range and 4.5-ps Resolution Fully-Synthesizable Time-to-Digital Converter with Quad-Edge Offset Cancellation
Author:
Affiliation:
1. Seoul National University,Dept. of Electrical and Computer Engineering,Korea
Funder
Samsung
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937646.pdf?arnumber=9937646
Reference29 articles.
1. A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology;kim;Dig Tech Papers VLSI Circuits (VLSIC) Symposium on,2014
2. A 9b, 1.12ps resolution 2.5b/stage pipelined time-to-digital converter in 65nm CMOS using time-register;kim;Dig Tech Papers VLSI Circuits (VLSIC) Symposium on,2013
3. Design and analysis of a robust all-digital clock generation system with a DLL-based TDC
4. A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
5. A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
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