A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing-Reference-Cited by-同舟云学术

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing

Published:2022-05-28 Issue: Volume: Page:
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Container-title:2022 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Kushwaha Dinesh¹,Sharma Aditya¹,Gupta Neha¹,Raj Ritik¹,Joshi Ashish¹,Mishra Jwalant²,Kohli Rajat³,Miryala Sandeep⁴,Joshi Rajiv⁵,Dasgupta Sudeb¹,Bulusu Anand¹

Affiliation:

1. Indian Institute of Technology,Department of Electronics and Communication,Roorkee,India

2. Intel Technology India Pvt. Ltd.,Bangalore,Karnataka,India

3. NXP Semiconductors,Bangalore,Karnataka,India

4. Brookhaven National Laboratory,Upton,NY,USA,11973

5. Thomas J. Watson Research Center,Yorktown Heights,NY,USA,10598

Funder

Semiconductor Research Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937908.pdf?arnumber=9937908

Reference27 articles.

1. A 42pJ/decision 3.12TOPS/W robust in-memory machine learning classifier with on-chip training

2. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array

3. A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

4. CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

5. A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors

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