A 20-24-GHz DPSSPLL with Charge-Domain Bandwidth Optimization Scheme Achieving 61.3-fs RMS Jitter and -253-dB FoMJitter
Author:
Affiliation:
1. The Hong Kong University of Science and Technology,Hong Kong
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10528947/10528954/10529091.pdf?arnumber=10529091
Reference6 articles.
1. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur
2. A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL
3. A 24-30 GHz Cascaded QPLL Achieving 56.8-fs RMS Jitter and −248.6-dB FoMjitter
4. 17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and −250dB FoM
5. An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and –252 dB FoM
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