A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs-Reference-Cited by-同舟云学术

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A 20Gb/s QPSK Receiver with Mixed-Signal Carrier, Timing, and Data Recovery Using 3-bit ADCs

Published:2024-04-21 Issue: Volume: Page:1-2
ISSN:
Container-title:2024 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Kubo Shunichi¹,Gendai Yuji¹,Miura Satoshi¹,Hara Shinsuke²,Tanoi Satoru²,Kasarnatsu Akifumi²,Yoshida Takeshi³,Tanaka Satoshi³,Arnakawa Shuhei³,Fujishlrna Minoru³

Affiliation:

1. THine Electronics, Inc.

2. National Institute of Information and Communications Technology

3. Hiroshima University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10528947/10528954/10529075.pdf?arnumber=10529075

Reference7 articles.

1. A 15-Gb/s 8-PSK Demodulator With Comparator-Based Carrier Synchronization

2. An Analog Costas Loop MMIC in 130 nm SiGe BiCMOS Technology for Receiver Synchronization of QPSK and BPSK Modulated Signals;Bammidi;EuMIC,2021

3. A 272-GHz CMOS Analog BPSK/QPSK Demodulator for IEEE 802.15.3d

4. A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver

5. A 115–135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method

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